1. Technical Field
This invention relates generally to memory technology, and more particularly, to the protection of the active layer of a memory cell during processing steps undertaken on other elements, for example, copper vias.
2. Background Art
Generally, memory devices associated with computers and other electronic devices are employed to store and maintain information for the operation thereof. Typically, such a memory device includes an array of memory cells, wherein each memory cell can be accessed for programming, erasing, and reading thereof. Each memory cell maintains information in an “off” state or an “on” state, also referred to as “0” and “1” respectively, which can be read during the reading step of that memory cell.
As such electronic devices continue to be developed and improved, the amount of information required to be stored and maintained continues to increase. FIG. 1 illustrates a type of memory cell 30 which includes advantageous characteristics for meeting these needs. The memory cell 30 includes, for example, an electrode 32, a superionic layer 34 such as Cu2S on the electrode 32, an active layer 36 such as Cu2O or various polymers on the Cu2S layer 34, and an electrode 38 on the active layer 36. Initially, assuming that the memory cell 30 is unprogrammed, in order to program the memory cell 30, a negative voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an electrical potential Vpg (the “programming” electrical potential) is applied across the memory cell 30 from a higher to a lower potential in the direction from electrode 32 to electrode 38. This potential is sufficient to cause copper ions to be attracted from the superionic layer 34 toward the electrode 38 and into the active layer 36, causing the active layer 36 (and the overall memory cell 30) to be in a low-resistance or conductive state. Upon removal of such potential, the copper ions drawn into the active layer 36 during the programming step remain therein, so that the active layer 36 (and memory cell 30) remain in a conductive or low-resistance state.
In order to erase the memory cell, a positive voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an electrical potential Ver is applied across the memory cell 30 from a higher to a lower electrical potential in the reverse direction. This potential causes current to flow through the memory cell in the reverse direction, and is sufficient to cause copper ions to be repelled from the active layer 36 toward the electrode 32 and into the superionic layer 34, in turn causing the active layer 36 (and the overall memory cell 30) to be in a high-resistance or substantially non-conductive state. This state remains upon removal of such potential from the memory cell 30.
In reading the state of the memory cell 30, an electrical potential Vr is applied across the memory cell 30 from a higher to a lower electrical potential in the same direction as the electrical potential Vpg. This electrical potential is less than the electrical potential Vpg applied across the memory cell 30 for programming (see above). In this situation, if the memory cell 30 is programmed, the memory cell 30 will readily conduct current, indicating that the memory cell 30 is in its programmed state. If the memory cell 30 is not programmed, the memory cell 30 will not conduct current, indicating that the memory cell 30 is in its erased state.
FIGS. 2–14 illustrate a process for forming such memory cells along with conductive bodies or plugs in an electronic structure. Initially, and with reference to FIG. 2, a dielectric layer 50 is formed over and on a conductive metal layer 52, for example copper, the metal layer 52 having been patterned into metal lines 52A, 52B as shown. Using standard lithographic techniques, via openings 54, 56 are formed in and through the dielectric layer 50 over the metal lines 52A, 52B, communicating with the metal lines 52A, 52B respectively (FIG. 3). Next (FIG. 4), the openings 54, 56 are filled with conductive material (for example copper) to form copper bodies 58, 60 in the respective openings 54, 56, which copper bodies 58, 60 contact the respective metal lines 52A, 52B of the layer 52.
A hard mask 62, for example silicon nitride, is formed over and on the upper surface of the resulting structure, i.e., over the upper surfaces of the copper bodies 58, 60 and the dielectric layer 50 by any suitable method (FIG. 5). Using standard lithographic techniques, portions of the hard mask 62 are removed to provide a remaining hard mask portion 64 overlying the copper body 58 but leaving the copper body 60 exposed (FIG. 6). Next, with reference to FIG. 7, the top surface of the copper body 60 is etched to form a recess 66 within the opening 56, the copper body 58 being protected therefrom by the hard mask portion 64 thereover.
A tantalum-containing layer 68 is deposited over and on the resulting structure (FIG. 8), i.e., over and on the exposed portions of the dielectric 50, the hard mask portion 64, and the copper body 60, filling in the recess 66 formed in the previous step. A polishing step then undertaken to remove all of the layer 68 except that portion 70 in the recess 66, and to remove the hard mask portion 64, leaving a cap 70 over the copper body 60 so as to form a conductive body 72 including the copper body 60 and cap 70 on and over the copper body 60, and planarizing the overall structure (FIG. 9). The copper body 58 itself forms a conductive body.
With reference to FIGS. 10 and 11, a memory structure 74 is formed over the copper body 58. In furtherance thereof, a passive layer 76 (FIG. 10), for example, Cu2S2, may be formed using sulfidation techniques, gas phase reactions, implantation, deposition, or any other suitable technique. This results in the passive layer 76 being on the copper body 58. As illustrated in FIG. 11, an active layer 78, which may be organic or inorganic material, is formed on and over the passive layer 76 by any suitable technique, including, for example, spin on techniques, chemical vapor deposition, and the like.
Prior to providing connections to the conductive body 72 and the active layer 78, a cleaning step 80 is undertaken to remove native oxide 82 which has formed on the conductive body 72 by contact with the air (FIG. 12). This is done to ensure that a conductive layer formed on and over the structure will provide proper ohmic contact with the conductive body 72. This step of removal oxidation may be achieved by argon sputter etching, which forcefully removes the oxide 82 from the exposed cap 70 of the conductive body 72. Next, a conductive metal layer 84, for example, aluminum, is provided on and over the resulting structure (FIG. 13), and is patterned (using standard lithographic techniques) into metal lines 84A, 84B, metal line 84A being on and over the active layer 78 and over the memory structure 74, and metal line 84B being on and over the conductive body 72 (FIG. 14). The steps thus far shown and described form the overall electronic structure 86. The conductive body 58, passive layer 76, active layer 78, and metal line 84A make up the memory cell as previously shown and described, and the conductive body 72 forms an interconnect between the metal line 52B and metal line 84B.
The cleaning step as illustrated and described has been found necessary for providing proper ohmic contact between the conductive layer 84 and the conductive body 72. However, this process for removal of oxidation 82 from the conductive body 72, involving relatively violent physical bombardment of the oxide 82, is undertaken with the active layer 78 of the memory structure 72 exposed. This aggressive cleaning process, while effective in removing the oxide 82, may well damage the exposed active layer 78, degrading the performance of the completed memory cell or rendering it inoperative.
Therefore, what is needed is an approach wherein proper removal of surface oxidation from selected conductive bodies is achieved, meanwhile avoiding damage to the memory structure.